1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating the same; in particular, the invention relates to a semiconductor device with a recessed trench and a method of fabricating the same.
2. Descriptions of the Related Art
In the rapid growing semiconductor industry, various manufacturing processes and applied materials have been developed for enhancing the integration and efficiency of integrated circuits (IC). As the integration of integrated circuits is boosted, gaps among elements and conductive lines continue to decrease day by day. In current nano-scale manufacturing processes, all the elements and structures disposed on a semiconductor substrate are required to be in nano-scale. With the demand of a high IC integration into extremely small dimensional requirement, it is necessary to redesign or adjust the disposition of elements so that the expected functions can be achieved.
Taking a MOSFET (metal oxide semiconductor field effect transistor) as an example, as integrated circuits devices are continuously scaled down, the dimension of the gaps between the functional areas, such as the sources, drains and gates, reduces. In addition, the channel length formed between the source and drain region shortens as well. However, the shortening of the channel length may cause the so-called “short channel effect” and “punch through effect,” severely affecting the original functions of the transistor device.
In order to overcome the aforesaid problems caused by the shortening of the channel length, a semiconductor device with a recessed channel has been proposed. Accordingly, a recessed trench forms in the semiconductor substrate to produce a recessed channel with increased length and to further reduce the dimensions of the semiconductor device.
However, using a recessed trench to increase the length of a channel formed thereby still possesses some problems. The most serious problem is that the overlap area between the gate and the drain increases with the depth of the recessed trench. Referring to FIG. 1, which illustrates a semiconductor device with a recessed trench of the prior art, the semiconductor device comprises an overlap area 10, a gate 12, a recessed trench 14, a gate oxide layer 16, a covering and spacing layer 18, a drain 20, and a source 22. A channel will be formed beside the recessed trench 14 as shown by the dotted line. The increase in the overlap area 10 in the semiconductor device of the prior art increases not only the gate induced drain leakage (GIDL) but also the parasitic capacitance between the gate 12 and drain 20, and thus affects the performance of the semiconductor device.
It is the desire of the semiconductor industry to increase IC integration of a semiconductor device while maintaining its performance. The present invention provides a solution for the problems of the above-mentioned semiconductor devices.